2.5
Mar 20, 2022
2.0
Apr 11, 2017
Review
1.8
Mar 29, 2014
Review
1.7
Nov 26, 2012
Review
1.2
May 10, 2011
Review

What's new

v2.0 [Apr 11, 2017]
- Ability to build components that can be reused in another circuit. The new "Circuit Block Elements" (CBE) components are user-defined in terms of schematics, enclosed within a component symbol.
- You can create two kinds of file. "New Circuit" will create a circuit ".pbs" file (as in the previous versions), and "New Block" , instead, will generate an empty ".cbe" file.
- Animation of a circuit that includes a CBE.
- Timing Simulation of a circuit including a CBE.
- Modified size of Input/Output components.
- Component Library enhancements.
- Input Dip-Switches
- Input Hex Digit.
- Output LED Arrays.
- Test Points have been introduced to allow displaying of signals during the simulation, without having to insert bulky Output Components into the schematics.
- FPGA board support extended.
- The "Recently Opened Files" registration method has changed. Now it is compatible "multi-instance ", i.e. all the opened Deeds-DcS instances will benefit of the same list of previously opened files, although opened from "siblings" instances.
- A new viewing mode has been added. You can activate it using the new "Schematics Only" command, available under the View menu.
- Main tracks management.
- Fixed a bug: in the dialog of the initial value was possible to change thestart value of a track, even if the simulation was already started.

v1.8 [Mar 29, 2014]
- Internal file version has changed (to 1.024), so files saved with the current 1.80 Deeds version cannot be opened in previous versions. However, as usual, backward compatibility is maintained: current version can read all the previous versions’ files.
- Counter components have been modified: in the new counter family, the “Terminal Count” output (Tc) can be disabled. For compatibility reasons, the previous counter type parts (used until version 1.71) are still available, but have been moved to the obsolete components library (see the menu command: “Circuit/Components/Old Library”).
- The counters have two enable inputs: En (Enable count) e Et (Enable Terminal Count). When Et and En are both “high”, counting is enabled. When Et is “high”, Tc is always generated, even when counting is disabled. When En is “high”, counting and Tc are enabled only when Et is “high”, while Et is “low”, it disables both counting and the generation of Tc.
- Register components, except the "universal shift registers", have been modified. The old components have been moved to the obsolete components library.
- The PIPO, PISO and SIPO components are characterized by the addition of an “Enable” input ('E'). A few pins have changed position. An important change on the PISO registers: the load input LD is now ‘synchronous’ and ‘active high’.
- In the “Test on FPGA” expert window, the "Slow Clock Mode" and "Step by Step Mode" have been extended. Now it is possible to reach, when automatic execution is set, respectively, up to 100 clock cycles and 100 instructions per second.
- Fixed a bug, in the “Test on FPGA” expert window: erasing an association previously done, when the circuit file was closed, a non-recoverable error occurred.
- When a “simulation by animation” was running, printing the circuit produced either an empty or incomplete print. The problem has been fixed, by temporary disabling the animation during the print process.
- Now, if the d-DcS tries to read a file generated by a newer d-DcS version, the warning message says: 'Newer d-DcS file format! Download and install the last Deeds Version'.
- Regarding the VHDL export of a d-FsM file, a bug has been fixed. In order to avoid the generation of input/output names non-compliant with the VHDL rules, the d-FsM adds the initial string "o_" to all outputs, and the string "i_" to all inputs. In this way, the name will never be equal to a reserved VHDL identifier.

v1.7 [Nov 26, 2012]
· A new “Push-button” input component has been added. It is useful, during interactive animation, to represent not only a real push-button device, but also to simulate pulse-shaped input command signals (i.e.: system reset).
· User can define, as a property of the component, if the button is “high” or “low” when pressed. The push-button is pressed with a mouse click; it is depressed when the mouse button is released. In the timing diagram window, the new push-button input track is defined as a usual switch input track.
· With the introduction of the new component, Switch and Push-button icons have been changed to highlight the differences between the two input components (in the main menu, in the component bin, in the timing diagram window and in the FPGA assignment window).
· Internal file version has changed (to 1.023), so files saved with the current Deeds version could not be opened in previous version. However, as usual, backward compatibility is maintained: current version can read all the previous version files.
· Bug fix: “demultiplexer” type components label have been corrected as “Dex 1 -> 2”, “Dex 1 -> 4”, “Dex 1 -> 8” and “Dex 1 -> 16”.
· Bug fix: the “Rotate Component” buttons are now visible again (they disappeared from the previous version).
· Mouse wheel now controls the signal traces scroll up/down function.
· Bug fix: sometimes, closing the timing diagram window, the “focus” moved to another application, instead to go to the d-DcS main window. The problem has been corrected.

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